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ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
13 years 5 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen
WETICE
2000
IEEE
13 years 11 months ago
Reducing Software Security Risk through an Integrated Approach
This paper presents joint work by the California Institute of Technology’s Jet Propulsion Laboratory and the University of California at Davis (UC Davis) sponsored by the Nation...
David P. Gilliam, John C. Kelly, Matt Bishop
ICCAD
2003
IEEE
141views Hardware» more  ICCAD 2003»
14 years 21 days ago
An Enhanced Multilevel Algorithm for Circuit Placement
This paper presents several important enhancements to the recently published multilevel placement package mPL [12]. The improvements include (i) unconstrained quadratic relaxation...
Tony F. Chan, Jason Cong, Tim Kong, Joseph R. Shin...
ICS
2001
Tsinghua U.
13 years 12 months ago
Cache performance for multimedia applications
The caching behavior of multimedia applications has been described as having high instruction reference locality within small loops, very large working sets, and poor data cache p...
Nathan T. Slingerland, Alan Jay Smith
DAC
2004
ACM
14 years 8 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan