Sciweavers

271 search results - page 30 / 55
» Computer aided creativity and multicriteria optimization in ...
Sort
View
ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
14 years 28 days ago
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Pin...
VEE
2012
ACM
187views Virtualization» more  VEE 2012»
12 years 3 months ago
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support
Dynamic Binary Translators (DBT) and Dynamic Binary Optimization (DBO) by software are used widely for several reasons including performance, design simplification and virtualiza...
Demos Pavlou, Enric Gibert, Fernando Latorre, Anto...
DAC
2010
ACM
13 years 5 months ago
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation
Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates systemlev...
Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li
PPNA
2010
71views more  PPNA 2010»
13 years 6 months ago
SPACE: A lightweight collaborative caching for clusters
In this paper, we introduce Systematic P2P Aided Cache Enhancement or SPACE, a new collaboration scheme among clients in a computer cluster of a high performance computing facility...
Mohammad Mursalin Akon, Mohammad Towhidul Islam, X...
DAC
2004
ACM
13 years 11 months ago
Enabling energy efficiency in via-patterned gate array devices
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architecture...
R. Reed Taylor, Herman Schmit