271 search results - page 39 / 55 » Computer aided creativity and multicriteria optimization in ... |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Input vector control (IVC) technique utilizes the stack effect in CMOS circuit to apply the minimum leakage vector (MLV) to the circuit at the sleep mode to reduce leakage. Additi...
ISQED
2005
IEEE
14 years 1 months ago
2005
IEEE
Due to the rapid development of manufacturing process technology and tight marketing schedule, the chip design and manufacturing always work toward an integrated solution to achie...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
With process scaling, leakage power reduction has become one of the most important design concerns. Multi-threshold techniques have been used to reduce runtime leakage power witho...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...