Wire routing in a VLSI chip often requires minimization of wire-length as well as the number of intersections among multiple nets. Such an optimization problem is computationally ...
Rajeev Kumar, Pramod Kumar Singh, Bhargab B. Bhatt...
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
With the advent of deep sub-micron (DSM) era, floorplanning has become increasingly important in physical design process. In this paper we clarify a misunderstanding in using Lag...
Placement is one of the most important steps in the RTLto-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and syste...
Jason Cong, Tim Kong, Joseph R. Shinnerl, Min Xie,...
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters i...