1474 search results - page 212 / 295 » Computing in Memory Architectures for Digital Image Processi... |
ICPP
2003
IEEE
14 years 2 months ago
2003
IEEE
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
FPL
2003
Springer
14 years 2 months ago
2003
Springer
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
EUROPAR
2010
Springer
13 years 9 months ago
2010
Springer
Today, it is possible to associate multiple CPUs and multiple GPUs in a single shared memory architecture. Using these resources efficiently in a seamless way is a challenging issu...
HICSS
2003
IEEE
14 years 2 months ago
2003
IEEE
Video information, image processing and computer vision techniques are developing rapidly nowadays because of the availability of acquisition, processing and editing tools, which ...
IJCSA
2008
13 years 9 months ago
2008
Vector extensions for general purpose processors are an efficient feature to address the growing performance demand of multimedia and computer vision applications. Embedded proces...