312 search results - page 5 / 63 » Concurrent Analysis Techniques for Data Path Timing Optimiza... |
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
ASPDAC
2009
ACM
14 years 2 months ago
2009
ACM
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
AIPS
2009
13 years 8 months ago
2009
We provide a theoretical analysis of planning via Petri net unfolding, a novel technique for synthesising parallel plans. Parallel plans are generally valued for their execution f...
CODES
2007
IEEE
14 years 2 months ago
2007
IEEE
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
ESA
1998
Springer
13 years 12 months ago
1998
Springer
In this paper, we study a class of optimal path problems with the following phenomenon: The space complexity of the algorithms for reporting the lengths of single-source optimal pa...