Because of the rapidly shrinking dimensions in VLSI, transient and permanent faults arise and will continue to occur in the near future in increasing numbers. Since cryptographic c...
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
The paper presents a new technique for designing a concurrently checking combinational circuit. The technique is based on partitioning the circuit into two independent sub-circuit...
Osnat Keren, Ilya Levin, Vladimir Ostrovsky, Beni ...
We propose a non-intrusive methodology for concurrent fault detection in FSMs. The proposed method is similar to duplication, wherein a replica of the circuit acts as a predictor ...
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...