4299 search results - page 7 / 860 » Concurrent Test Generation |
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper proposes an efficient test methodology to test switches in a Network-on-Chip (NoC) architecture. A switch in an NoC consists of a number of ports and a router. Using th...
TCAD
2008
13 years 7 months ago
2008
The verification of a system-on-chip is challenging due to its high level of integration. Multiple components in a system can behave concurrently and compete for resources. Hence, ...
SIGSOFT
2010
ACM
13 years 5 months ago
2010
ACM
Concurrent programs are notoriously difficult to debug. We see two main reasons for this: 1) concurrency bugs are often difficult to reproduce, 2) traces of buggy concurrent execu...
ASPLOS
2010
ACM
14 years 2 months ago
2010
ACM
Debugging concurrent programs is difficult. This is primarily because the inherent non-determinism that arises because of scheduler interleavings makes it hard to easily reproduc...
ITC
2003
IEEE
14 years 19 days ago
2003
IEEE
Composite microsystems that integrate mechanical and fluidic components are fast emerging as the next generation of system-on-chip designs. As these systems become widespread in s...