18 search results - page 3 / 4 » Congestion Estimation with Buffer Planning in Floorplan Desi... |
DAC
1999
ACM
13 years 11 months ago
1999
ACM
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
SLIP
2005
ACM
14 years 27 days ago
2005
ACM
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
— Fast and accurate routing congestion estimation is essential for optimizations such as floorplanning, placement, buffering, and physical synthesis that need to avoid routing c...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
Wirelength estimation techniques typically contain a site density function that enumerates all possible path sites for each wirelength in an architecture and an occupation probabil...
ICCAD
2002
IEEE
14 years 9 days ago
2002
IEEE
Shrinking process geometries and the increasing use of IP components in SoC designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-c...