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DFT
2003
IEEE
64views VLSI» more  DFT 2003»
14 years 2 months ago
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...
DFT
2003
IEEE
113views VLSI» more  DFT 2003»
14 years 2 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
ICCAD
2003
IEEE
129views Hardware» more  ICCAD 2003»
14 years 2 months ago
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...
Ruibing Lu, Cheng-Kok Koh
INFOCOM
2003
IEEE
14 years 2 months ago
Optimal Bandwidth Reservation Schedule in Cellular Network
Abstract— Efficient bandwidth allocation strategy with simultaneous fulfillment of QoS requirement of a user in a mobile cellular network is still a critical and an important p...
Samrat Ganguly, B. R. Badrinath, Navin Goyal
INFOVIS
2003
IEEE
14 years 2 months ago
A Visual Workspace for Hybrid Multidimensional Scaling Algorithms
In visualising multidimensional data, it is well known that different types of data require different types of algorithms to process them. Data sets might be distinguished accordi...
Greg Ross, Matthew Chalmers