94 search results - page 4 / 19 » Control Independence in Trace Processors |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
— Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration r...
PDP
1997
IEEE
13 years 11 months ago
1997
IEEE
Event tracing and monitoring of parallel applications are difficult if each processor has its own unsynchronized clock. A survey is given on several strategies to generate a glob...
DSD
2010
IEEE
13 years 7 months ago
2010
IEEE
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
CONPAR
1992
13 years 11 months ago
1992
The Asynchronous Polycyclic Architecture (APA) is a new processor design for numerically intensive applications. APA resembles the VLIW architecture, in that it provides independen...
ICCD
2003
IEEE
14 years 4 months ago
2003
IEEE
There is a growing interest in the use of speculative multithreading to speed up the execution of a program. In speculative multithreading model, threads are extracted from a sequ...