28 search results - page 1 / 6 » Convex delay models for transistor sizing |
DAC
2000
ACM
14 years 8 months ago
2000
ACM
This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presente...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...
ICCAD
2002
IEEE
14 years 3 months ago
2002
IEEE
─ In this paper, we present Forge, an optimal algorithm for gate sizing using the Elmore delay model. The algorithm utilizes Lagrangian relaxation with a fast gradient-based pre-...
ISLPED
1995
ACM
13 years 10 months ago
1995
ACM
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
TCAD
1998
13 years 6 months ago
1998
— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...