275 search results - page 14 / 55 » Core architecture optimization for heterogeneous chip multip... |
ASPDAC
2009
ACM
13 years 6 months ago
2009
ACM
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
HIPEAC
2011
Springer
12 years 8 months ago
2011
Springer
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
ASPDAC
2009
ACM
14 years 1 months ago
2009
ACM
– The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Mo...
CODES
2007
IEEE
14 years 3 months ago
2007
IEEE
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
— Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of po...