275 search results - page 23 / 55 » Core architecture optimization for heterogeneous chip multip... |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consump...
IEEEPACT
2009
IEEE
13 years 6 months ago
2009
IEEE
Efficiently using the hardware capabilities of the Cell processor, a heterogeneous chip multiprocessor that uses several levels of parallelism to deliver high performance, and bei...
HIPC
2007
Springer
14 years 2 months ago
2007
Springer
: The Cell is a heterogeneous multi-core processor, which has eight co-processors, called SPEs. The SPEs can access a common shared main memory through DMA, and each SPE can direct...
ESTIMEDIA
2008
Springer
13 years 10 months ago
2008
Springer
The relentless increase in multimedia embedded system application requirements as well as improvements in IC design technology have motivated the deployment of chip multiprocessor ...
HPCA
2006
IEEE
14 years 9 months ago
2006
IEEE
This paper explores the multi-dimensional design space for chip multiprocessors, exploring the inter-related variables of core count, pipeline depth, superscalar width, L2 cache s...