275 search results - page 34 / 55 » Core architecture optimization for heterogeneous chip multip... |
EUROPAR
2009
Springer
14 years 3 months ago
2009
Springer
Moore’s Law suggests that the number of processing cores on a single chip increases exponentially. The future performance increases will be mainly extracted from thread-level par...
DDECS
2007
IEEE
14 years 3 months ago
2007
IEEE
—Current system-on-chip implementations integrate IP blocks from different vendors. Typical problems are incompatibility and integration overheads. This paper presents a case stu...
DAC
2006
ACM
13 years 10 months ago
2006
ACM
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
DATE
2010
IEEE
13 years 7 months ago
2010
IEEE
— Applications like 4G baseband modem require single-chip implementation to meet the integration and power consumption requirements. These applications demand a high computing pe...
MICRO
2007
IEEE
14 years 2 months ago
2007
IEEE
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...