275 search results - page 45 / 55 » Core architecture optimization for heterogeneous chip multip... |
ISPASS
2009
IEEE
14 years 3 months ago
2009
IEEE
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
HPCA
2003
IEEE
14 years 9 months ago
2003
IEEE
Scalability of applications on distributed sharedmemory (DSM) multiprocessors is limited by communication overheads. At some point, using more processors to increase parallelism y...
ISPAN
2005
IEEE
14 years 2 months ago
2005
IEEE
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
DAC
2004
ACM
14 years 9 months ago
2004
ACM
To meet conflicting flexibility, performance and cost constraints of demanding signal processing applications, future designs in this domain will contain an increasing number of a...
CPHYSICS
2010
13 years 8 months ago
2010
In this paper, a programming model is presented which enables scalable parallel performance on multi-core shared memory architectures. The model has been developed for application...