548 search results - page 1 / 110 » Core-Selectability in Chip Multiprocessors |
IEEEPACT
2009
IEEE
13 years 8 months ago
2009
IEEE
Abstract--The centralized structures necessary for the extraction of instruction-level parallelism (ILP) are consuming progressively smaller portions of the total die area of chip ...
DSN
2011
IEEE
12 years 10 months ago
2011
IEEE
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
TVLSI
2010
13 years 5 months ago
2010
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
NOCS
2010
IEEE
13 years 9 months ago
2010
IEEE
A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global cloc...
HPCA
2011
IEEE
13 years 2 months ago
2011
IEEE
Translation Lookaside Buffers (TLBs) are critical to processor performance. Much past research has addressed uniprocessor TLBs, lowering access times and miss rates. However, as c...