548 search results - page 20 / 110 » Core-Selectability in Chip Multiprocessors |
139
Voted
SC
2009
ACM
15 years 10 months ago
2009
ACM
Existing cache partitioning schemes are designed in a manner oblivious to the implicit processor partitioning enforced by the operating system. This paper examines an operating sy...
128
Voted
IEEEPACT
2009
IEEE
15 years 10 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
133
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IEEEPACT
2009
IEEE
15 years 10 months ago
2009
IEEE
Translation Lookaside Buffers (TLBs) are a staple in modern computer systems and have a significant impact on overall system performance. Numerous prior studies have addressed TL...
147
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IISWC
2008
IEEE
15 years 10 months ago
2008
IEEE
The PARSEC benchmark suite was recently released and has been adopted by a significant number of users within a short amount of time. This new collection of workloads is not yet ...
122
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ISCA
2008
IEEE
15 years 10 months ago
2008
IEEE
Within-die process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported. In this ...