Sciweavers

237 search results - page 29 / 48
» Cost-Efficient Memory Architecture Design of NAND Flash Memo...
Sort
View
GLVLSI
2010
IEEE
149views VLSI» more  GLVLSI 2010»
13 years 9 months ago
Lightweight runtime control flow analysis for adaptive loop caching
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...
Marisha Rawlins, Ann Gordon-Ross
AINA
2008
IEEE
14 years 2 months ago
WS-BPEL Process Compiler for Resource-Constrained Embedded Systems
Process management and workflow systems play an important role in the composition of services in business as well as automation environments. Processes are designed using tools a...
Hendrik Bohn, Andreas Bobek, Frank Golatowski
DAC
1999
ACM
14 years 8 months ago
A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems
We present a novel approach that minimizes the power consumption of embedded core-based systems through hardware/software partitioning. Our approach is based on the idea of mapping...
Jörg Henkel
CODES
2007
IEEE
14 years 2 months ago
A data protection unit for NoC-based architectures
Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related...
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic...
LCTRTS
2010
Springer
14 years 2 months ago
Operation and data mapping for CGRAs with multi-bank memory
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunh...