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ICCD
2003
IEEE
113views Hardware» more  ICCD 2003»
14 years 23 days ago
Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity
As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-o...
Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nour...
MBEES
2010
13 years 5 months ago
Test Case Integration: From Components to Systems
In a component-based development approach system integration generally implies the packaging and deployment of a group of software components on hardware units, possibly hiding th...
Bernhard Schätz, Christian Pfaller
DATE
2003
IEEE
96views Hardware» more  DATE 2003»
14 years 24 days ago
Test Data Compression: The System Integrator's Perspective
Test data compression (TDC) is a promising low-cost methodology for System-on-a-Chip (SOC) test. This is due to the fact that it can reduce not only the volume of test data but al...
Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola N...
DATE
2003
IEEE
90views Hardware» more  DATE 2003»
14 years 24 days ago
Extending JTAG for Testing Signal Integrity in SoCs
As the technology is shrinking and the working frequency is going into multi gigahertz range, the issues related to interconnect testing are becoming more dominant. Specifically,...
Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nour...
VTS
2005
IEEE
95views Hardware» more  VTS 2005»
14 years 1 months ago
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...
Baosheng Wang, Yuejian Wu, Josh Yang, André...