58 search results - page 6 / 12 » Critical path analysis using a dynamically bounded delay mod... |
TKDE
2011
13 years 3 months ago
2011
—It is essential to process real-time data service requests such as stock quotes and trade transactions in a timely manner using fresh data, which represent the current real worl...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper addresses a constrained two-terminal reliability measure referred to as Distance Reliability (DR) between the source node u and the destination node I with the shortest...
ASPDAC
2009
ACM
14 years 2 months ago
2009
ACM
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...
MICRO
2002
IEEE
14 years 1 months ago
2002
IEEE
In this paper we present an approach to boosting performance and tolerating latency by deferring non-critical instructions into a deferred queue for later processing. As such, ins...