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» Crosstalk Reduction by Transistor Sizing
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DAC
2007
ACM
14 years 8 months ago
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization
Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep tran...
De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih...
ISLPED
2007
ACM
138views Hardware» more  ISLPED 2007»
13 years 9 months ago
Power optimal MTCMOS repeater insertion for global buses
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
Hanif Fatemi, Behnam Amelifard, Massoud Pedram
ASPDAC
2004
ACM
149views Hardware» more  ASPDAC 2004»
14 years 27 days ago
A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design
With the exponential reduction in the scaling of feature size, inter-wire coupling capacitance becomes the dominant part of load capacitance. Two problems are introduced by coupli...
Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, J...
ASPDAC
2005
ACM
92views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Sleep transistor sizing using timing criticality and temporal currents
— Power gating is a circuit technique that enables high performance and low power operation. One of the challenges in power gating is sizing the sleep transistor which is used to...
Anand Ramalingam, Bin Zhang, Anirudh Devgan, David...
ISPD
2004
ACM
120views Hardware» more  ISPD 2004»
14 years 27 days ago
On optimal physical synthesis of sleep transistors
Considering the voltage drop constraint over a distributed model for power/ground (P/G) network, we study the following two problems for physical synthesis of sleep transistors: t...
Changbo Long, Jinjun Xiong, Lei He