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CODES
2004
IEEE
14 years 10 days ago
A novel deadlock avoidance algorithm and its hardware implementation
This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provi...
Jaehwan Lee, Vincent John Mooney III
DAC
2004
ACM
14 years 9 months ago
Multi-profile based code compression
Code compression has been shown to be an effective technique to reduce code size in memory constrained embedded systems. It has also been used as a way to increase cache hit ratio...
Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Ce...
ACMMSP
2006
ACM
260views Hardware» more  ACMMSP 2006»
14 years 2 months ago
Seven at one stroke: results from a cache-oblivious paradigm for scalable matrix algorithms
A blossoming paradigm for block-recursive matrix algorithms is presented that, at once, attains excellent performance measured by • time, • TLB misses, • L1 misses, • L2 m...
Michael D. Adams, David S. Wise
ASPLOS
2012
ACM
12 years 4 months ago
Architectural support for hypervisor-secure virtualization
Virtualization has become a standard part of many computer systems. A key part of virtualization is the all-powerful hypervisor which manages the physical platform and can access ...
Jakub Szefer, Ruby B. Lee
ISCA
2010
IEEE
229views Hardware» more  ISCA 2010»
13 years 7 months ago
Understanding sources of inefficiency in general-purpose chips
Due to their high volume, general-purpose processors, and now chip multiprocessors (CMPs), are much more cost effective than ASICs, but lag significantly in terms of performance a...
Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Az...