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CODES
2009
IEEE
14 years 16 days ago
Building heterogeneous reconfigurable systems with a hardware microkernel
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a softwarelike ...
Jason Agron, David L. Andrews
ISCA
2006
IEEE
162views Hardware» more  ISCA 2006»
14 years 2 months ago
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
Feihui Li, Chrysostomos Nicopoulos, Thomas D. Rich...
ICPADS
2006
IEEE
14 years 2 months ago
SPM Conscious Loop Scheduling for Embedded Chip Multiprocessors
One of the major factors that can potentially slow down widespread use of embedded chip multiprocessors is lack of efficient software support. In particular, automated code paral...
Liping Xue, Mahmut T. Kandemir, Guangyu Chen, Tayl...
DATE
2008
IEEE
113views Hardware» more  DATE 2008»
14 years 3 months ago
Compositional, dynamic cache management for embedded chip multiprocessors
This paper proposes a dynamic cache repartitioning technique that enhances compositionality on platforms executing media applications with multiple utilization scenarios. The repa...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
14 years 19 days ago
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...