43 search results - page 4 / 9 » Cycle count accurate memory modeling in system level design |
DAC
2004
ACM
14 years 24 days ago
2004
ACM
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Increase in system level modeling has given rise to a need for efficient functional validation of models above cycle accurate level. This paper presents a technique for comparing...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
IESS
2009
Springer
13 years 5 months ago
2009
Springer
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
ASAP
2005
IEEE
14 years 1 months ago
2005
IEEE
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...