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» Cycle count accurate memory modeling in system level design
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VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
14 years 7 months ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...
TCAD
2008
167views more  TCAD 2008»
13 years 7 months ago
System-Level Dynamic Thermal Management for High-Performance Microprocessors
Abstract--Thermal issues are fast becoming major design constraints in high-performance systems. Temperature variations adversely affect system reliability and prompt worst-case de...
Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K....
TECS
2008
119views more  TECS 2008»
13 years 7 months ago
Fast exploration of bus-based communication architectures at the CCATB abstraction
straction SUDEEP PASRICHA and NIKIL DUTT University of California, Irvine and MOHAMED BEN-ROMDHANE Newport Media Inc. Currently, system-on-chip (SoC) designs are becoming increasin...
Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane
SIGMETRICS
1998
ACM
13 years 11 months ago
Predicting MPEG Execution Times
This paper reports on a set of experiments that measure the amount of CPU processing needed to decode MPEGcompressed video in software. These experiments were designed to discover...
Andy C. Bavier, Allen Brady Montz, Larry L. Peters...
ASPDAC
2009
ACM
139views Hardware» more  ASPDAC 2009»
14 years 1 months ago
Hardware-dependent software synthesis for many-core embedded systems
Abstract— This paper presents synthesis of Hardware Dependent Software (HdS) for multicore and many-core designs using Embedded System Environment (ESE). ESE is a tool set, devel...
Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho...