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ISCA
2009
IEEE
230views Hardware» more  ISCA 2009»
14 years 2 months ago
Architecting phase change memory as a scalable dram alternative
Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as DRAM. In contrast, phase change memory (PCM)...
Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burg...
ISCA
2009
IEEE
180views Hardware» more  ISCA 2009»
14 years 2 months ago
Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices
The widespread use of multicore processors has dramatically increased the demands on high bandwidth and large capacity from memory systems. In a conventional DDR2/DDR3 DRAM memory...
Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zh...
ISCA
2012
IEEE
237views Hardware» more  ISCA 2012»
11 years 10 months ago
BOOM: Enabling mobile memory based low-power server DIMMs
To address the real-time processing needs of large and growing amounts of data, modern software increasingly uses main memory as the primary data store for critical information. T...
Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar...
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
13 years 11 months ago
Use ECP, not ECC, for hard failures in resistive memories
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...
Stuart E. Schechter, Gabriel H. Loh, Karin Straus,...
SC
2009
ACM
14 years 2 months ago
Flexible cache error protection using an ECC FIFO
We present ECC FIFO, a mechanism enabling two-tiered last-level cache error protection using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of addin...
Doe Hyun Yoon, Mattan Erez