71 search results - page 8 / 15 » Data Memory Design Considering Effective Bitwidth for Low-En... |
EMSOFT
2005
Springer
14 years 1 months ago
2005
Springer
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
CASES
2007
ACM
13 years 11 months ago
2007
ACM
We propose a technique which leverages configurable data caches to address the problem of cache interference in multitasking embedded systems. Data caches are often necessary to p...
RTSS
2007
IEEE
14 years 2 months ago
2007
IEEE
Recently, cheap and large capacity non-volatile memory such as flash memory is rapidly replacing disks not only in embedded systems, but also in high performance servers. Unlike ...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
ESTIMEDIA
2005
Springer
14 years 1 months ago
2005
Springer
Portable embedded systems require diligence in managing their energy consumption. Thus, power efficient processors coupled with onchip memories (e.g. caches, scratchpads) are the...