1602 search results - page 141 / 321 » Database Architectures for New Hardware |
ISCAS
2003
IEEE
14 years 2 months ago
2003
IEEE
Abstract - A comprehensive study of ultra high-speed currentmode logic (CML) buffers and regenerative CML latches will be illustrated. A new design procedure to systematically desi...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
The new standard DRM for digital radio broadcast in AM band requires integrated devices for radio receivers at low cost and very low power consumption. A chipset is currently desi...
FPL
2001
Springer
14 years 1 months ago
2001
Springer
System and processor architectures depend on changes in technology. Looking ahead as die density and speed increase, power consumption and on chip interconnection delay become incr...
ICCD
2007
IEEE
14 years 6 months ago
2007
IEEE
This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume lit...
ICCD
2000
IEEE
14 years 6 months ago
2000
IEEE
We introduce a new register file architecture that provides both row-wise and column-wise accesses, thus allowing partitioned instructions to be used in columnwise processing with...