1602 search results - page 170 / 321 » Database Architectures for New Hardware |
MICRO
2000
IEEE
13 years 8 months ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
SOCA
2010
IEEE
13 years 6 months ago
2010
IEEE
While modern CPUs offer an increasing number of cores with shared caches, prevailing execution engines for business processes, workflows, or Web service compositions have not been ...
ICCD
2007
IEEE
14 years 6 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
The increasing power dissipation of current processors and processor cores constrains design options, increases packaging and cooling costs, increases power delivery costs, and de...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
— Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of po...