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FPL
2007
Springer
100views Hardware» more  FPL 2007»
14 years 3 months ago
Clock-Aware Placement for FPGAs
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
Julien Lamoureux, Steven J. E. Wilton
DATE
2003
IEEE
117views Hardware» more  DATE 2003»
14 years 2 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
WOB
2004
120views Bioinformatics» more  WOB 2004»
13 years 10 months ago
Reconfigurable Systems for Sequence Alignment and for General Dynamic Programming
ABSTRACT. Reconfigurable systolic arrays can be adapted to efficiently resolve a wide spectrum of computational problems; parallelism is naturally explored in systolic arrays and r...
Ricardo P. Jacobi, Mauricio Ayala-Rincón, L...
ISCA
2008
IEEE
136views Hardware» more  ISCA 2008»
13 years 9 months ago
The Design and Performance of a Bare PC Web Server
There is an increasing need for new Web server architectures that are application-centric, simple, small, and pervasive in nature. In this paper, we present a novel architecture f...
Long He, Ramesh K. Karne, Alexander L. Wijesinha
ASPLOS
2006
ACM
14 years 3 months ago
Introspective 3D chips
While the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. To deal with the complexit...
Shashidhar Mysore, Banit Agrawal, Navin Srivastava...