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DATE
2008
IEEE
148views Hardware» more  DATE 2008»
14 years 3 months ago
Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications
Stream processing applications such as image signal processing demand high throughput. However, customers increasingly demand runtime flexibility in their designs, which cannot b...
Mark Muir, Tughrul Arslan, Iain Lindsay
ASYNC
2007
IEEE
154views Hardware» more  ASYNC 2007»
14 years 3 months ago
Design of a High-Speed Asynchronous Turbo Decoder
This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-perf...
Pankaj Golani, Georgios D. Dimou, Mallika Prakash,...
DSD
2006
IEEE
159views Hardware» more  DSD 2006»
14 years 2 months ago
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions
Region concept helps to accommodate cores larger than the tile size in mesh topology NoC architectures. In addition, it offers many new opportunities for NoC design, as well as pr...
Rickard Holsmark, Maurizio Palesi, Shashi Kumar
DATE
2005
IEEE
135views Hardware» more  DATE 2005»
14 years 2 months ago
Compositional Memory Systems for Multimedia Communicating Tasks
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
WMPI
2004
ACM
14 years 2 months ago
Selective main memory compression by identifying program phase changes
During a program’s runtime, the stack and data segments of the main memory often contain much redundancy, which makes them good candidates for compression. Compression and decomp...
Doron Nakar, Shlomo Weiss