1602 search results - page 252 / 321 » Database Architectures for New Hardware |
MICRO
2006
IEEE
14 years 2 months ago
2006
IEEE
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
Abstract--This paper summarizes a special session on multicore/multi-processor system-on-chip (MPSoC) programming challenges. Wireless multimedia terminals are among the key driver...
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
RAS
2008
13 years 8 months ago
2008
Robot projects are often evolutionary dead ends, with the software and hardware they produce disappearing without trace afterwards. Common causes include dependencies on uncommon ...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...