We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Abstract--This paper summarizes a special session on multicore/multi-processor system-on-chip (MPSoC) programming challenges. Wireless multimedia terminals are among the key driver...
Rainer Leupers, Lothar Thiele, Xiaoning Nie, Bart ...
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Robot projects are often evolutionary dead ends, with the software and hardware they produce disappearing without trace afterwards. Common causes include dependencies on uncommon ...
Paul M. Fitzpatrick, Giorgio Metta, Lorenzo Natale
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...