1602 search results - page 38 / 321 » Database Architectures for New Hardware |
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
COMPUTING
2004
13 years 7 months ago
2004
The presented image registration method uses a regularized gradient flow to correlate the intensities in two images. Thereby, an energy functional is successively minimized by des...
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
- Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach ...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
At-speed testing of GHz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost, high-quality self-test m...
ISCAS
2002
IEEE
14 years 16 days ago
2002
IEEE
In this paper, we focus on developing a new relaxed Givens rotations (RGR)-RLS algorithm and the corresponding RGR-RLS systolic array. The resulting algorithm and architecture pos...