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SBACPAD
2008
IEEE
249views Hardware» more  SBACPAD 2008»
14 years 2 months ago
Processing Neocognitron of Face Recognition on High Performance Environment Based on GPU with CUDA Architecture
This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an ar...
Gustavo Poli, José Hiroki Saito, Joã...
DATE
2003
IEEE
89views Hardware» more  DATE 2003»
14 years 27 days ago
Heterogeneous Programmable Logic Block Architectures
In this poster, we propose four new heterogeneous programmable logic blocks (PLBs) consisting of a combination of various sizes of look up tables (LUTs), multiplexers (MUXes), and...
Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Cheta...
ASPDAC
2000
ACM
95views Hardware» more  ASPDAC 2000»
13 years 12 months ago
Retargetable estimation scheme for DSP architecture selection
— Given the recent wave of innovation and diversification in digital signal processor (DSP) architecture, the need for quickly evaluating the true potential of considered archite...
Naji Ghazal, A. Richard Newton, Jan M. Rabaey
MSS
2000
IEEE
84views Hardware» more  MSS 2000»
13 years 12 months ago
A Portable Tape Driver Architecture
This paper describes a new architecture for device drivers for tape drives attached to UNIX-like systems. The design goals are presented, some current architectures are measured a...
Curtis Anderson
MTDT
1999
IEEE
88views Hardware» more  MTDT 1999»
13 years 12 months ago
Computing in Memory Architectures for Digital Image Processing
Continuing improvements in semiconductor fabrication density are enabling new classes of System-on-aChip architectures that combine extensive processing logic and high-density mem...
Luke Roth, Lee D. Coraor, David L. Landis, Paul T....