This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an ar...
In this poster, we propose four new heterogeneous programmable logic blocks (PLBs) consisting of a combination of various sizes of look up tables (LUTs), multiplexers (MUXes), and...
Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Cheta...
— Given the recent wave of innovation and diversification in digital signal processor (DSP) architecture, the need for quickly evaluating the true potential of considered archite...
This paper describes a new architecture for device drivers for tape drives attached to UNIX-like systems. The design goals are presented, some current architectures are measured a...
Continuing improvements in semiconductor fabrication density are enabling new classes of System-on-aChip architectures that combine extensive processing logic and high-density mem...
Luke Roth, Lee D. Coraor, David L. Landis, Paul T....