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ICCD
1999
IEEE
86views Hardware» more  ICCD 1999»
13 years 12 months ago
Evaluation of Computing in Memory Architectures for Digital Image Processing Applications
Continuing improvements in semiconductor density are enabling new classes of System-on-a-Chip architectures that combine extensive processing logic and high-density memory. Many o...
David L. Landis, Paul T. Hulina, Scott Deno, Luke ...
DATE
2009
IEEE
159views Hardware» more  DATE 2009»
14 years 2 months ago
Design and implementation of a database filter for BLAST acceleration
— BLAST is a very popular Computational Biology algorithm. Since it is computationally expensive it is a natural target for acceleration research, and many reconfigurable archite...
Panagiotis Afratis, Constantinos Galanakis, Euripi...
DATE
2009
IEEE
155views Hardware» more  DATE 2009»
14 years 2 months ago
Using non-volatile memory to save energy in servers
Abstract—Recent breakthroughs in circuit and process technology have enabled new usage models for non-volatile memory technologies such as Flash and phase change RAM (PCRAM) in t...
David Roberts, Taeho Kgil, Trevor N. Mudge
VLDB
2001
ACM
138views Database» more  VLDB 2001»
14 years 1 days ago
Operating System Extensions for the Teradata Parallel VLDB
This paper describes the new architecture for supporting the Teradata commercial VLDB on several new operating environments. We start with an overview of the Teradata database sof...
John Catozzi, Sorana Rabinovici
DATE
2006
IEEE
134views Hardware» more  DATE 2006»
14 years 1 months ago
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory a...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...