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ISCAS
2005
IEEE
136views Hardware» more  ISCAS 2005»
14 years 1 months ago
Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders
— Low-Density Parity-Check Convolutional Codes (LDPC-CCs) are an attractive alternative to their block-oriented counterparts, LDPC-BCs. In this paper, we introduce these codes an...
Ramkrishna Swamy, Stephen Bates, Tyler L. Brandon
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 2 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
3DIC
2009
IEEE
184views Hardware» more  3DIC 2009»
14 years 2 months ago
Architectural evaluation of 3D stacked RRAM caches
The first memristor, originally theorized by Dr. Leon Chua in 1971, was identified by a team at HP Labs in 2008. This new fundamental circuit element is unique in that its resis...
Dean L. Lewis, HsienHsin S. Lee
ISCA
1998
IEEE
144views Hardware» more  ISCA 1998»
13 years 12 months ago
Declustered Disk Array Architectures with Optimal and Near-Optimal Parallelism
This paper investigates the placement of data and parity on redundant disk arrays. Declustered organizations have been traditionally used to achieve fast reconstruction of a faile...
Guillermo A. Alvarez, Walter A. Burkhard, Larry J....
VLDB
2001
ACM
96views Database» more  VLDB 2001»
14 years 4 days ago
Architectures for Internal Web Services Deployment
There is a new emerging world of web services. In this world, services will be combined in innovative ways to form elaborate services out of building blocks of other services. Thi...
Oded Shmueli