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122
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DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
112
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DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
Errors in timing closure process during the physical design stage may result in systematic silicon failures, such as scan chain hold time violations, which prohibit the test of ma...
DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
Functional unit shutdown based on MTCMOS devices is effective for leakage reduction in aggressively scaled technologies. However, the applicability of MTCMOS-based shutdown in a s...
125
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DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
145
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DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
The problem of diagnosis – or locating the source of an error or fault – occurs in several areas of Computer Aided Design, such as dynamic verification, property checking, eq...