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DATE
2006
IEEE
93views Hardware» more  DATE 2006»
15 years 10 months ago
Restructuring field layouts for embedded memory systems
In many computer systems with large data computations, the delay of memory access is one of the major performance bottlenecks. In this paper, we propose an enhanced field remappi...
Keoncheol Shin, Jungeun Kim, Seonggun Kim, Hwansoo...
DATE
2006
IEEE
151views Hardware» more  DATE 2006»
15 years 10 months ago
40Gbps de-layered silicon protocol engine for TCP record
We present a de-layered protocol engine for termination of 40Gbps TCP connections using a reconfigurable FPGA silicon platform. This protocol engine is designed for a planned att...
H. Shrikumar
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
15 years 10 months ago
Performance analysis of greedy shapers in real-time systems
— Traffic shaping is a well-known technique in the area of networking and is proven to reduce global buffer requirements and end-to-end delays in networked systems. Due to these...
Ernesto Wandeler, Alexander Maxiaguine, Lothar Thi...
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
15 years 10 months ago
Functional Validation of System Level Static Scheduling
Increase in system level modeling has given rise to a need for efficient functional validation of models above cycle accurate level. This paper presents a technique for comparing...
Samar Abdi, Daniel D. Gajski
DATE
2005
IEEE
132views Hardware» more  DATE 2005»
15 years 10 months ago
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage
In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a s...
Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylve...