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2005
IEEE
117views Hardware» more  DATE 2005»
15 years 10 months ago
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...
Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew...
DATE
2005
IEEE
158views Hardware» more  DATE 2005»
15 years 10 months ago
Scheduling of Soft Real-Time Systems for Context-Aware Applications
Context-aware applications pose new challenges, including a need for new computational models, uncertainty management, and efficient optimization under uncertainty. Uncertainty c...
Jennifer L. Wong, Weiping Liao, Fei Li, Lei He, Mi...
DATE
2003
IEEE
112views Hardware» more  DATE 2003»
15 years 9 months ago
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0
The concept of a SOC platform architecture introduces the concept of a communication infrastructure. In the transaction-level a finite set of architecture components (memories, ar...
Marco Caldari, Massimo Conti, Massimo Coppola, Ste...
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DATE
2003
IEEE
109views Hardware» more  DATE 2003»
15 years 9 months ago
A Novel Metric for Interconnect Architecture Performance
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Mud...
DATE
2003
IEEE
96views Hardware» more  DATE 2003»
15 years 9 months ago
Time Domain Multiplexed TAM: Implementation and Comparison
One of the difficult problems which core-based systemon-chip (SoC) designs face is test access. For testing the cores in a SoC, a special mechanism is required, since they are no...
Zahra Sadat Ebadi, André Ivanov