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DATE
2008
IEEE
153views Hardware» more  DATE 2008»
14 years 4 months ago
An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications
Novel reconfigurable computing platforms enable efficient realizations of complex signal processing applications by allowing exploitation of parallelization resulting in high thro...
Sankalita Saha, Jason Schlessman, Sebastian Puthen...
DATE
2008
IEEE
105views Hardware» more  DATE 2008»
14 years 4 months ago
Comparison of Boolean Satisfiability Encodings on FPGA Detailed Routing Problems
We compare 12 new encodings for representing of FPGA detailed routing problems as equivalent Boolean Satisfiability (SAT) problems against the only 2 previously used encodings. We...
Miroslav N. Velev, Ping Gao 0002
DATE
2006
IEEE
122views Hardware» more  DATE 2006»
14 years 4 months ago
Power analysis of mobile 3D graphics
— The world of 3D graphics, until recently restricted to high-end workstations and game consoles, is rapidly expanding into the domain of mobile platforms such as cellular phones...
Bren Mochocki, Kanishka Lahiri, Srihari Cadambi
DATE
2010
IEEE
107views Hardware» more  DATE 2010»
14 years 3 months ago
An error-correcting unordered code and hardware support for robust asynchronous global communication
A new delay-insensitive data encoding scheme for global asynchronous communication is introduced. The goal of this work is to combine the timing-robustness of delay-insensitive (i....
Melinda Y. Agyekum, Steven M. Nowick
DATE
2010
IEEE
157views Hardware» more  DATE 2010»
14 years 3 months ago
RMOT: Recursion in model order for task execution time estimation in a software pipeline
Abstract—This paper addresses the problem of execution time estimation for tasks in a software pipeline independent of the application structure or the underlying architecture. A...
Nabeel Iqbal, M. A. Siddique, Jörg Henkel