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DATE
2009
IEEE
113views Hardware» more  DATE 2009»
14 years 3 months ago
Incorporating graceful degradation into embedded system design
In this work, the focus is put on the behavior of a system in case a fault occurs that disables the system from executing its applications. Instead of executing a random subset of...
Michael Glaß, Martin Lukasiewycz, Christian ...
DATE
2009
IEEE
98views Hardware» more  DATE 2009»
14 years 3 months ago
Test architecture design and optimization for three-dimensional SoCs
Core-based system-on-chips (SoCs) fabricated on threedimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimizat...
Li Jiang, Lin Huang, Qiang Xu
DATE
2007
IEEE
108views Hardware» more  DATE 2007»
14 years 3 months ago
Evaluation of design for reliability techniques in embedded flash memories
Non-volatile Flash memories are becoming more and more popular in Systems-on-Chip (SoC). Embedded Flash (eFlash) memories are based on the well-known floatinggate transistor conce...
Benoît Godard, Jean Michel Daga, Lionel Torr...
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
14 years 2 months ago
ASIP design and synthesis for non linear filtering in image processing
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
Luca Fanucci, Michele Cassiano, Sergio Saponara, D...
DATE
2006
IEEE
128views Hardware» more  DATE 2006»
14 years 2 months ago
Efficient link capacity and QoS design for network-on-chip
This paper addresses the allocation of link capacities in the automated design process of a network-on-chip based system. Communication resource costs are minimized under Quality-...
Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israe...