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105
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DATE
2006
IEEE
83views Hardware» more  DATE 2006»
15 years 9 months ago
What lies between design intent coverage and model checking?
Practitioners of formal property verification often work around the capacity limitations of formal verification tools by breaking down properties into smaller properties that ca...
Sayantan Das, Prasenjit Basu, Pallab Dasgupta, P. ...
DATE
2005
IEEE
164views Hardware» more  DATE 2005»
15 years 9 months ago
Automotive System Design - Challenges and Potential
Increasing functional and non-functional requirements in automotive electric /electronic vehicle development will significantly enhance the integration of novel functions in the e...
Harald Heinecke
123
Voted
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
15 years 9 months ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...
108
Voted
DATE
2005
IEEE
235views Hardware» more  DATE 2005»
15 years 9 months ago
Challenges in Embedded Memory Design and Test
Both the number of embedded memories, as well as the total embedded memory content in our chips is growing steadily. Time for chip designers, EDA makers, and test engineers to upd...
Erik Jan Marinissen, Betty Prince, Doris Keitel-Sc...
122
Voted
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
15 years 9 months ago
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach
— A novel power attack resistant cryptosystem is presented in this paper. Security in digital computing and communication is becoming increasingly important. Design techniques th...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...