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JUCS
2000
120views more  JUCS 2000»
13 years 7 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
HPCA
2006
IEEE
14 years 8 months ago
A decoupled KILO-instruction processor
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
Miquel Pericàs, Adrián Cristal, Rube...
ISCA
1999
IEEE
110views Hardware» more  ISCA 1999»
13 years 12 months ago
Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
PLDI
2010
ACM
14 years 20 days ago
Z-rays: divide arrays and conquer speed and flexibility
Arrays are the ubiquitous organization for indexed data. Throughout programming language evolution, implementations have laid out arrays contiguously in memory. This layout is pro...
Jennifer B. Sartor, Stephen M. Blackburn, Daniel F...
SAS
2010
Springer
262views Formal Methods» more  SAS 2010»
13 years 6 months ago
Concurrent Separation Logic for Pipelined Parallelization
Recent innovations in automatic parallelizing compilers are showing impressive speedups on multicore processors using shared memory with asynchronous channels. We have formulated a...
Christian J. Bell, Andrew W. Appel, David Walker