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ICCAD
1998
IEEE
75views Hardware» more  ICCAD 1998»
14 years 24 days ago
A fast, accurate, and non-statistical method for fault coverage estimation
We present a fast, dynamic fault coverage estimation technique for sequential circuits that achieves high degrees of accuracy by signi cantly reducing the number of injected fault...
Michael S. Hsiao
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
14 years 2 months ago
Implicit and Exact Path Delay Fault Grading in Sequential Circuits
1 The first path implicit and exact non–robust path delay fault grading technique for non–scan sequential circuits is presented. Non enumerative exact coverage is obtained, b...
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, S...
VLSID
1997
IEEE
135views VLSI» more  VLSID 1997»
14 years 22 days ago
Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation
The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as e...
Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxen...
ICCAD
1997
IEEE
108views Hardware» more  ICCAD 1997»
14 years 23 days ago
Fault simulation of interconnect opens in digital CMOS circuits
We describe a highly accurate but e cient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations f...
Haluk Konuk
ICCAD
2006
IEEE
183views Hardware» more  ICCAD 2006»
14 years 5 months ago
Soft error derating computation in sequential circuits
Soft error tolerant design becomes more crucial due to exponential increase in the vulnerability of computer systems to soft errors. Accurate estimation of soft error rate (SER), ...
Hossein Asadi, Mehdi Baradaran Tahoori