We present a fast, dynamic fault coverage estimation technique for sequential circuits that achieves high degrees of accuracy by signi cantly reducing the number of injected fault...
1 The first path implicit and exact non–robust path delay fault grading technique for non–scan sequential circuits is presented. Non enumerative exact coverage is obtained, b...
The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as e...
Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxen...
We describe a highly accurate but e cient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations f...
Soft error tolerant design becomes more crucial due to exponential increase in the vulnerability of computer systems to soft errors. Accurate estimation of soft error rate (SER), ...