34 search results - page 5 / 7 » Deductive Fault Simulation for Asynchronous Sequential Circu... |
DAC
1995
ACM
14 years 3 days ago
1995
ACM
Retiming has been proposed as an optimizationstep forsequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so chang...
DATE
1998
IEEE
14 years 25 days ago
1998
IEEE
We extend the subsequence removal technique to provide signi cantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to ident...
FPL
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is fre...
ET
2000
13 years 8 months ago
2000
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
VTS
1997
IEEE
14 years 23 days ago
1997
IEEE
Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a sm...