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» Defect tolerance for nanocomputer architecture
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NOCS
2010
IEEE
13 years 5 months ago
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
Abstract--The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face...
Samuel Rodrigo, Jose Flich, Antoni Roca, Simone Me...
DAC
2006
ACM
14 years 8 months ago
Timing-based delay test for screening small delay defects
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
VLSID
2007
IEEE
131views VLSI» more  VLSID 2007»
14 years 8 months ago
Defect-Aware Synthesis of Droplet-Based Microfluidic Biochips
Recent advances in microfluidics technology have led to the emergence of miniaturized biochip devices for biochemical analysis. A promising category of microfluidic biochips relie...
Tao Xu, Krishnendu Chakrabarty, Fei Su
ISCA
2010
IEEE
340views Hardware» more  ISCA 2010»
14 years 20 days ago
Necromancer: enhancing system throughput by animating dead cores
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike onchip caches, which can be efficiently prot...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
DAC
2010
ACM
13 years 6 months ago
An error tolerance scheme for 3D CMOS imagers
A three-dimensional (3D) CMOS imager constructed by stacking a pixel array of backside illuminated sensors, an analog-to-digital converter (ADC) array, and an image signal process...
Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, ...