19 search results - page 3 / 4 » Delay-Insensitive Carry-Lookahead Adders |
CORR
2010
Springer
13 years 2 months ago
2010
Springer
Combinational or Classical logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its correspon...
DFT
2006
IEEE
13 years 11 months ago
2006
IEEE
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
ISMVL
1999
IEEE
13 years 11 months ago
1999
IEEE
We introduce a new implementation of a ternary adder with four inputs and two outputs. This ternary adder reduces the number of digits in a multiplication compared with a binary m...
ASAP
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipat...
GLVLSI
2003
IEEE
14 years 21 days ago
2003
IEEE
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...