86 search results - page 13 / 18 » Delay-Reduced Combinational Logic Synthesis using Multiplexe... |
GLVLSI
2007
IEEE
14 years 4 months ago
2007
IEEE
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
ASPDAC
2009
ACM
14 years 4 months ago
2009
ACM
- With increasing availability of predefined IP (Intellectual Properties) blocks and inexpensive microprocessors, embedded system designers are faced with more design choices than ...
JSAC
2011
13 years 4 months ago
2011
This paper investigates the issue of dynamic resource allocation (DRA) in the context of multiuser cognitive radio networks. We present a general framework adopting generalized si...
DAC
2008
ACM
14 years 10 months ago
2008
ACM
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
SIGGRAPH
1993
ACM
14 years 1 months ago
1993
ACM
Image-space simplifications have been used to accelerate the calculation of computer graphic images since the dawn of visual simulation. Texture mapping has been used to provide a...