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CODES
2007
IEEE
15 years 10 months ago
Secure FPGA circuits using controlled placement and routing
In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an ex...
Pengyuan Yu, Patrick Schaumont
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DATE
2007
IEEE
145views Hardware» more  DATE 2007»
15 years 10 months ago
Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508
This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the...
Riccardo Mariani, Gabriele Boschi, Federico Colucc...
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
15 years 10 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
IAT
2007
IEEE
15 years 10 months ago
Agent-Based Network Intrusion Detection System
The paper presents security platform based on agents as an efficient and robust solution for high-performance intrusion detection system designed for deployment on highspeed netw...
Vojtech Krmicek, Pavel Celeda, Martin Rehák...
ICNS
2007
IEEE
15 years 10 months ago
Towards System-level Optimization for High Performance Unified Threat Management
To build holistic protection against complex and blended network threats, multiple security features need to be integrated into a unified security architecture, which requires in ...
Yaxuan Qi, Baohua Yang, Bo Xu, Jun Li